1. Field of the Invention
The invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device having two transistors sharing a same gate structure and a method of forming the same.
2. Description of the Prior Art
Conventional planar metal-oxide-semiconductor (MOS) transistors have difficulty when scaling down to 65 nm and below. For overcoming the process limitation, three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (FinFET) has been developed to replace planar MOS transistors. Since the three-dimensional structure of a FinFET increases the overlapping area between the gate and the fin-shaped structure of the silicon substrate, the channel region can therefore be more effectively controlled. This way, the drain-induced barrier lowering (DIBL) effect and the short channel effect are reduced accordingly.
However, integration of a metal gate and contact plugs still faces some issues in conventional FinFET fabrication. Hence, how to improve the current FinFET fabrication and structure for resolving such issue has become an important task in this field.